Companding pulse code modulation system

ABSTRACT

A plurality of cascaded attenuators, comparators, and switching means develops from an analogue signal a set of successive &#39;&#39;&#39;&#39;one&#39;&#39;&#39;&#39; digits and an adjacent set of successive &#39;&#39;&#39;&#39;zero&#39;&#39;&#39;&#39; digits. These digits correlate with the P.M.C. code as determined by a computer.

United States Patent [191 80m) 80 5,?) g 50%) Jun. 2 11 .n L115.

Mauduech 5] May 22, 1973 COMPANDING PULSE CODE 235/177 MODULATION SYSTEM[76] Inventor: Robert R. Mauduech, 7, rue du [56] References CitedDocteur Roux, Perros-Guirec, UNITED STATES PATENTS France 3,452,2976/1969 Kelly et a1. ..332/9 [22] Filed: Sept. 8, 1969 3,473,132 10/1969Keeler et a1.

[21] Appl' 855381 Primary Examiner-Donald J. Yusko AttorneyAbra.ham A.Saffitz Foreign Application Priori Data ty [57] ABSTRACT Sept. 11, 1968France ..68165786 A plurality of cascaded attenuators, comparators, and[52 us. C1. ..32s/3s 328/142 329/109 swiching means devebps mm anahgueSignal a 333/14 set of successive one digits and an adjacent set ofsuccessive zero digits. These digits correlate with 51 I t.C1. E 5 L ofSearch 325/38 the P.M.C. code as determined by a computer.

1 Claim, 6 Drawing Figures L fig g 5m 2 gag/ml 1 B19 302 204 505 875 1081: 7% /2l?,) ,213) my) (2-2,) (3/8,) 7/ T 815%) 530 82] w 824 825 707708 m 515 l M 25. L1; Y.... 2 ra z) 70 M 74 2) A a r 3 c B 91 92 95 8 997 T: g "F i 95 97 D/E/TAL 1 [WWI/UH? ,1 v; 1 /7 90 /7 91w) Patented May22,1973 3,735,264

5 Sheets-Sheet 5 Robert R. MAUDUECl-l COMPANDING PULSE CODE MODULATIONSYSTEM The present invention relates to nonlinear pulse code modulationsystems and coders employing amplitude compression and to decodersemploying amplitude expansion. More particularly this invention relatesto coders and decoders utilizing discrete cascaded attenuators eachhaving two values of attenuation.

Pulse code modulation or PCM communication systems employ an encoder atthe transmitting terminal to convert the magnitude and polarity of asample of an intelligence signal, such as an audio signal, to a group ofpulses in accordance with a predetermined code.

These pulse groups are the transmitted signal and must be translated atthe receiver into a representation of the original signal. A decoder isprovided at the receiver to reconstruct the signal sample. The samplemay then be recombined with adjacent samples to recover the originalsignal.

It is well known that the coding of weak analog signals should beproduced with high precision; on the contrary, a definite tolerance isacceptable for the coding of substantial analog signals. Accordingly, itis advantageous to employ PCM systems giving unequal weights to thequantizing steps of the so-called compression and expansion type.

The compression law commonly recognized as the most favorable toquantify the analog signals to be coded is that which, expressed inrelative variables, is represented by the expression symmetrical withrespect to zero:

in which:

y p x p maz.

p denoting the order of the quantification step,

counted in the direction of increasing amplitudes; n the total number ofquantification steps; V, the instantaneous value of the signal amplitudeto be coded, applied to the input point of the encoder, for the step ofthe order p;

V the maximum value of the signal amplitude;

p, a dimensionless parameter whose optimum value is According to thecompression principle of the invention, nine points a b c d efg h aretaken on the curve defined by equation (1), these points being thelimits of eight quantizing steps and between these points the curve isreplaced by straight lines. The coordinates of these nine points are thefollowing:

F0 L .L i i 2 l l 1 I28 64 32 l6 s 4 2 l l 2 l 2 Z 1 y a 4 a z 8 4 8 ifit is assumed that V, 1024 and n 64. It is to be noticed that all thecoordinate values of the equations (2) are multiples of 8.

Each of the straight lines joining two adjacent points on curve (1) isdivided into eight equal segments by seven points the coordinates ofwhich form an arithmetical progression whose ratio is the eighth part ofthe coordinate difference between said two adjacent points.

The following table I gives the abscissae and ordinates of the 64 points(65 if terminal point h is included), 8 on the curve and 56 on thebroken line approximating the curve.

Ordinate p Abscissa V ,i of the steps of the steps T T 000 001 OlO 01110] Ill 0= 000 0 l 2 3 4 5 6 7 l 001 8 9 l0 ll l2 13 l4- l5 2 010 l6 1820 22 24- 26 28 30 3= ()ll 32 36 4-0 4-4 4-8 52 56 60 4- 100 64 72 8O 8896 104 112 5 101 128 14-4 176 192 208 224 240 6= 110 256 288 320 352384- 416 448 4-80 7 ll 5l2 576 640 704 768 832 896 960 The value of pfor each of the quantizing steps can be expressed in an octal binarysystem including two octal digits each formed of three bits:

The first octal digit represents the ordinate of a given point on thecurve and the second octal digit the serial number of a given point onthe straight line starting from said given point on the curve. Forexample the quantizing step defined by points i andj has for itsordinate The arithmetical ratio of the abscissa values of Table V l isnot the same throughout the table; it is l in lines 0 and l, 2 in line2, 4 in line 3, 8 in line 4, 16 in line 5, 32 in line 6 and 64 in line7.

The arithmetical ratio doubles from a line to the following,respectively from line 2 to line seven but it does not double betweenlines 0 and l.

The relationship between the abscissa V, and the ordinate p (T T T X YZ), the sign bit being disregarded, is:

V,= (l X Y Z) 2 Twin-1) except for the V, values of line 0. For example,let us search after the value of V, for p (01 l)(l10) 30 which complieswith table I.

For line 1 of table I equation (3) becomes:

The analog values of V, are converted into binary code according aspecial codification. The coded values comprise ten bits (the sign bitdisregarded):

V,=AB CDEFGXYZ As already said, the ordinate of a quantizing step isexpressed in binary code by two groups of three bits (T T T and (X Y Z).The group (T, T, T defines groups, of steps and the group (X Y Z) thestep in the group. I

The step groups have different heights while the steps I.

The encoder of the invention compares the sample to be coded into PCMbits and the same sample divided by the successive powers of two topredetermined voltages in a set of cascaded comparators which generatesof a given group have the same height. i 5 the bits A G; it codes theresidue of said sample after In the code of V the three last bits (X YZ) are the the comparisons in a linear coder which generates the same asin the code of the step number p. The other bits (X Y Z) and convertsthe special code (A B C D E digits A B C D E F G are bits but do notform a binary F G) into a binary code (T T, T The PCM code of number inthe usual meaning. They form numbers havthe sample is then (T T, T X YZ). The compression ing one digits at the left hand side and zero digitsat the proper is implemented during the conversion from (A right handside, the ones and the zeroes never being in- B C D E F G) to (T T Tterlaced and the number of ones being equal to the dec- Com andinencoders and decoders using switchable imal number equal to (T T T Thecodes of V are and cascaded attenuators forming an attenuationnettabulated in the following table II. work, each being designed forattenuating, if switched,

TABLE II Ordinate of Abscissa range of the grou; of the group of Code ofStep Steps ABCDEFGXYZ I 2 T! 0 0 0 O (8 6) 0 0 i) 0 0 0 0 variableaccording 0 0 1 (8-e)(16e) 1 0 0 0 0 0 0 to the 1 serial 0 l 0(l6-e)(32-e) 1 l O 0 0 0 0 number of the 0 1 1 (32e)(64'e) l 1 1 0 0 O 0step in the group 1 0 0 (641)-(128-5) 1 1 1 1 0 0 0 1 l 0 (256E)"(5l2 1l 1 1 1 1 0 1 l l 15l2'-E)-11024-) l 1 l l l l l The relationshipbetween the bits T T T and the an input signal to a level which is afunction of its rank bits A, B, C, D, E, F, G are the following: in thenetwork are known in the prior art. In said com- T D 35 panding systemsthe attenuation network is a nonlinear network and it may be said thatin this system T B D F (5) compression and expansion is performedanalogically. In the invention on the contrary the compression is per- AB C D E F G fonned digitally and results from digital relationships 40between the bits of a sample coded in a special code A 1 2 3 and thebits of the corresponding compressed sample expressed in a binary code.B T The invention will be grasped more readily upon C Tl T2 T3 readingthe following detailed description given with reference to theaccompanying drawings, in which D I FIG. 1 illustrates a compressioncoder according to E T1 T3 .1. T1 T2 the invention;

F FIGS. 2 and 3 show diagrams of elements employed T1 T2 in the coder ofFIG. 1; G T T T FIG. 4 illustrates an expansion decoder according to theinvention; For example let us assume that D 96 FIG. 5 illustrates amodified form of the compression coder of the invention; and V 1 1 1 1 00 1 O 0 FIG. 6 represents a compression curve, useful for exth plainingthe principles of the invention as disclosed in the introductory part. AB C D X 1 FIG. 1 illustrates a compression coder according to E=F=G=Y=Z=o the lnv entlon. In this figure the reference numeral 10 designatesan Equauons E v amplitude sampler and pulse stretcher receiving the an-T1 l alog signals to be coded; it may be of any known type; at itsoutput point, it delivers constant amplitude pulses T2 0 whose durationis at least equal to the duration of the T 0 coding operation. Circuit10 is connected to polarity which complies with table I.

detector20 which is simultaneously a rectifier and the sign stage of theencoder. It gives at one of its outputs the analog signal to be codedwith always a positive polarity and at its second output 21 a bit Swhich is zero or unity depending on whether the polarity of the incomingsignal is negative or positive. This detector may be of known type; apreferred form of embodiment will be described in the following,however.

Circuit 30 is the comparator network comprising seven stagesinterconnected by switchable dividers-bytwo. Circuit 30 generates thebits A, B, C, D, E, F, G. Circuit 40 is a logical circuit which derivesT,, T,, T, from A G and 50 is a subtracter arranged at the output pointof the comparator network 30 so that the linear coder 60 receives theappropriate voltages at its input.

The comparator network 30 comprises six series arms of which the first301, connected to the input terminal 30,,, has a resistance (2 R,)whereas the other five 303, 305, 307, 309, 311 have resistances of thevalue (R,) and six shunt arms 302, 304, 306, 308, 310, 312 having thesame resistance 2 R,.

These shunt arms equally comprise switches 314, 316, 318, 320, 322, 324,which may, for example, consist of transistors operating by passing fromthe blocked condition to the saturated condition. These switches, openin the idle state, are closed thanks to the voltages which appear at theoutput terminals of the comparators 313, 315, 317, 319, 321, 323, 325allocated respectively to the switches 314, 316, 318, 320, 322, 324.

These comparators, which are all identical, are differential amplifiersof known type, possessing a high input impedance. The first inputterminals of comparators 313, 315, 317, 319, 321, 323, are all connectedto a source of constant voltage having a value slightly smaller than 16quantizing steps. Only the first input terminal of comparator 325 isconnected to a source of constant voltage having a value slightlysmaller than 8 quantizing steps. The second input terminal of comparator313 is connected to the input terminal 30,, of the comparator network.The second input terminals of comparators 315, 317, 319, 321, 323, 325,are connected respectively to the points 31 36 common to the adjacentseries resistances of the network.

E denoting the sample applied at the input terminals 30,, 30, of theline, this will be compared to the voltage (16-6) in the comparator 313(e is a very small quantity).

If E (16-6), no signal issues from the comparator, the switches 314,316, 318, 320, 322, 324 remain open, and no coded signal appears at theterminals 303, 304, 30 30 307, 30

As for the comparator 325, a distinction may be drawn between two cases:

1. If 0 E (8e), the voltage at the point 36 is equal to E since none ofthe shunt arms of the network is in operation and moreover, theimpedance connected to the output terminals 30 30 is very great comparedto 7 R, the sum of the resistances 301, 303, 305, 307, 309, 311.

The comparator 325 compares the voltage E to the voltage (8 e) and, as aresult, a zero pulse issuesfrom at the output terminal 30, of thecomparator 325.

The first two lines of table 11 are thus justified. The case of thethird line of table II will now be considered, that is:

The comparator 313 transmits a signal B l which appears at the terminal30 Moreover, this signal causes the closing of the switch 314, whichplaces shunt arm 302 in operation.

Owing to the fact that the output impedance of the polarity detector 20is very low, the voltage which appears at 31, at the terminals of theresistance 302, is equal to E 2, and since the comparator 315 does nottransmit a signal, so that C O at the terminal 30,.

The comparator 325 is driven at 36 by the voltage E 2 and according tothe preceding, the signal A 1 appears at the terminal 30. The third lineof table II is thus justified.

(32-e) E (64-e) the comparators 313, 315 come into action, the switches314 and 316 close, and B l, C= 1. A voltage E 4 appears at the point 32,owing to the fact that according to the theorem of Thevenin, theimpedance of the source having 31 as its terminal, is equal to 2 R,(resistance 303 resistances 301 and 302 in parallel).

The comparator 325 is thus driven at 36 by voltages comprised within therange:

(8 e) E/4 (16 e) and consequently transmits a signal A l. The fourthline of table II is thus justified. The same reasoning is applicable tothe following lines of the same table ll.

Logical circuit 40 establishes the Boolean functions As apparent fromFIG. 1, digit T, which is identical to digit D is obtained at terminal40,. The function ED is generated by AND gate 44 and inverter 43. The ORgate 45 receiving and F at its input terminals generates digit T, whichappears at terminal 40 The function AEis established by the AND gate 48and the inverter 47. Cl is formed by the AND gate 46 and the inverter43; EF is formed by the AND gate 41 and the inverter 42. The OR gate 49receiving AF, CD, EFand G, provides the binary element T at its outputterminal 40 At the output terminals 30 30 of the comparator network 30voltages comprised within the range 0 (8 e) appear for the signals ofthe line 0 of the table II and voltages comprised within the range (8 e)(l6 e) for the signals of all the other lines 1 7 of the table. So thatit may transmit the three right-hand bits X, Y, Z at its outputterminals 60,, 60 60 the linear coder 60 should receive, at its inputterminal 60 voltages comprised within the range 0 (8 e) irrespec-.

tive of the amplitude range which includes the sample to be coded. Theknown device 50 interposed between the comparator network 30 and thecoder 60, renders it possible to obtain this result.

Device 50 essentially comprises an operational amplifier 50 and a switch51 controlled by the output of comparator 325. If V,, is the voltagesupplied by the switch 51 and if V is the voltage at the input terminalof the coder 60, the voltage at the terminal I of the amplifier 52, is:

If V is the voltage at the output terminal 30 of the network 30, thevoltage at the terminal D of the amplifier 52, is:

Since, very approximately, D V,

V V V V (V V By way of example, FIG. 2 shows an embodiment of the switch51. It is of known type and lacks any special feature.

By way of example, FIG. 3 shows an embodiment of the polarity or signdetector 20. Irrespective of the polarity of the sample to be codedwhich is applied to the input terminals 20,, a corresponding sample ofthe same amplitude and of always positive polarity appears at the outputterminals 20 20., of amplifier 21. At its output terminal 20 moreover,the comparator 28 provides the sign bit S which is zero when the sampleto be coded is of negative polarity, and one if it is of positivepolarity. This bit S 1 equally controls the set of switches 27 which,when they are closed, connect the direct input of amplifier 21 to groundthrough resis tance 23; the sample to be coded appears at the terminalsof resistance 26, that is to say at the inverting input .of amplifier 21which has a gain of 2. When the switches 27 are open, the voltageappears at D and the gain then amounts to +2.

FIG. 4 illustrates the diagram of an expansion decoder according to theinvention. Its function is to reconstitute, from the one sign bit andsix code bits it receives, a direct voltage of appropriate polaritywhose value is proportional to the binary number represented by theaforesaid six code bits.

In FIG. 4, 70 is a ladder network comprising two series arms 703, 705having the resistance R three shunt arms 702, 704, 706 having theresistance 2 R and a load resistance 701 having the value 2 R The shuntarms 702, 704, 706 are equipped, respectively, with switches 707, 708,709. These switches are controlled, respectively, by the bits Z, Y, Xapplied to terminals 70 70 70,. When in the idle state (Z 0, Y= 0, X 0)they connect the shunt as 702, 704, 706 to ground and a zero voltageprevails between terminals 70 70 A voltage having a value proportionalto the value of the combination X Y Z appears between these sameterminals as soon as the switches connect one or more of the shunt arms702, 704, 706 to the terminal 71 of a source 71 of direct current, whoseother terminal 71 is grounded. The internal resistance of this source isnegligible compared to those of the resistances (2 R Circuit 80comprises an attenuator network preceded by an amplifier whose inputterminals are connected to the output terminals 70 70 of the assembly70. The said circuit 80 may be considered as a variable gain amplifier.I

The ladder network is of identical structure to that of the assembly 30of the coder of FIG. 1. It comprises a series arm 801 with theresistance 2 R five series arms 803, 805, 807, 809, 811 having theresistance R,, six shunt arms 802, 804, 806, 808, 810, 812 having theresistance 2 R,; each of these latter arms is equipped with switches 820to 825 (transistors in blocked-saturated operation) controlledrespectively by the signals G, F, E, D, C, B reconstituted from thebinary elements T T T, by means of the assembly of logical circuits 90.This assembly 90 establishes the Boolean relationships (6) cited in theforegoing.

When the signals G, F, E, D, C, B are equal to zero, all the shunt armsof the ladder network come into play and the said network has a maximumattenuation. For example, if B l, the switch 825 deactivates the arm 812and the attenuation of the network decreases by six decibels, Inconclusion, the operation of the attenuator network of the assembly 80is reciprocal to that of the attenuator network of the assembly 30.

The variable gain amplifier is supplied, from the terminals 70 70 of theassembly 70, through a voltage divider 814, 815. The switch 813, of thesame type as that of FIG. 2, activates the arm 815 when it is actuatedby the signal A l reconstituted by application of the signals T T T tothe input terminals of an OR gate 91.

The device situated at the output of the attenuator network andcontrolled by the sign bit S, reverses the voltage provided by the linewhen S 1. Its amplification factor may be equal to plus or minus two asin the device of FIG. 3.

FIG. 5 illustrates a modified form of the compression encoder of theinvention. In this coder, the reference voltages are less numerous thanin that of FIG. 1; this is advantageous since the diversity of thereference sources, by multiplying the number of switches increases theprobability of errors, unless these switches are built with great care.When the values of the quantizing steps are of the order of a fewmillivolts, the said errors are comparable to the actual samples to becoded.

In FIG. 5, the elements in common with those of the encoder of FIG. Ibear the same reference numerals. The feature of the encoder of FIG. 5is that the attenuator network, sequentially dividing the voltages, hasbeen split into two identical parts 30 30 separated by an amplifierassembly 30 The part 30, supplies the signals E, F, G. The part 30supplies the signals B, C, D.

The comparators of the two parts 30 30 have their first input terminalsconnected to one and the same reference source whose voltage is equal to(128 6) steps.

The amplifying system 30 effects a double reversal of the voltageissuing from the circuit 30, and amplifies the same eight times beforebeing attenuated by the circuit 30 The signal which issues from thecircuit 30 is applied to the four-stage linear coder 60 which may be ofany known type. The first stage of the coder delivers the signal A at60,. The three other stages of the coder 60 deliver the binary elementsX, Y, Z, respectively at 60,,

tudes of the original samples to be coded are distributed into amplituderanges forming the widths of quantizing steps which exponentiallyincrease with amplitude and the amplitudes of the correspondingcompressed samples being distributed into successive equal amplituderanges forming the heights of said quantizing steps and defined bybinary digit combination signals expressed in a PCM code, comprising anetwork of identical cascaded attenuators, each of said attenuatorshaving a first state in which its attenuation is zero and a second statein which its attenuation is two, means for applying to the input of saidnetwork samples of said analog signals, a plurality of comparatorsrespectively comparing to a predetermined voltage the signals at theoutputs of the attenuators, a plurality of switching means respectivelycontrolled by said comparators and selectively controlling the states ofthe attenuators,

whereby the output signals of the comparators form binary digitcombination signals representative of said samples expressed in aspecial code comprising a set of successive one digits and an adjacentset of successive zero digits in which the number of one digits is equalto the decimal number of the quantizing step and the number of zerodigits is equal to the complement of said decimal number to the totalnumber of said quantizing steps, the digits of the special codecombination representative of an original sample being correlated to thedigits of the PCM code combination representative of the correspondingcompressed sample by linear relationships, and a computer deriving thedigits of the PCM code combination representative of the compressedsample from the digits of the special code combination representative ofthe corresponding original sample.

1. Compression coder for coding original samples of analog signals intoPCM signals in which the amplitudes of the original samples to be codedare distributed into amplitude ranges forming the widths of quantizingsteps which exponentially increase with amplitude and the amplitudes ofthe corresponding compressed samples being distributed into successiveequal amplitude ranges forming the heights of said quantizing steps anddefined by binary digit combination signals expressed in a PCM code,comprising a network of identical cascaded attenuators, each of saidattenuators having a first state in which its attenuation is zero and asecond state in which its attenuation is two, means for applying to theinput of said network samples of said analog signals, a plurality ofcomparators respectively comparing to a predetermined voltage thesignals at the outputs of the attenuators, a plurality of switchingmeans respectively controlled by said comparators and selectivelycontrolling the states of the attenuators, whereby the output signals ofthe comparators form binary digit combination signals representative ofsaid samples expressed in a special code comprising a set of successiveone digits and an adjacent set of successive zero digits in which thenumber of one digits is equal to the decimal number of the quantizingstep and the number of zero digits is equal to the complement of saiddecimal number to the total number of said quantizing steps, the digitsof the special code combination representative of an original samplebeing correlated to the digits of the PCM code combinationrepresentative of the corresponding compressed sample by linearrelationships, and a computer deriving the digits of the PCM codecombination representative of the compressed sample from the digits ofthe special code combination representative of the correspondingoriginal sample.